Integrated circuits for converting a high voltage level to a low voltage level

ABSTRACT

An integrated circuit includes a high side driver and a low side driver. The low side driver is electrically coupled with the high side driver. A circuit is electrically coupled with the high side driver and a first node between the high side driver and the low side driver. The circuit is configured to substantially turn off the high side driver if the high side driver leaves a cutoff region of the high side driver during a tri-state mode.

TECHNICAL FIELD

The present disclosure relates generally to the field of semiconductortechnology, and more particularly, to integrated circuits for convertinga high voltage level to a low voltage level.

BACKGROUND OF THE DISCLOSURE

Light-emitting diodes (LEDs) are semiconductor light sources and havebeen used to replace conventional fluorescent lamp sources.Conventionally, LEDs are semiconductor diodes made from compoundmaterials. If the diodes are forward biased, electrons supplied from anode recombine with holes supplied from another node, releasing energyin the form of photons. By selecting the compound materials, emissioncolors of the LEDs can vary from red to blue.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the numbers and dimensions of the various features may bearbitrarily increased or reduced for clarity of discussion.

FIG. 1A is a schematic drawing illustrating a first exemplary integratedcircuit for converting a high voltage level to a low voltage level.

FIG. 1B is a schematic flowchart illustrating a method of operating anexemplary integrated circuit for converting a high voltage level to alow voltage level.

FIG. 2 is a schematic drawing illustrating a second exemplary integratedcircuit for converting a high voltage level to a low voltage level.

FIG. 3 is a schematic drawing illustrating waveforms of various signals.

FIG. 4 is a schematic drawing illustrating a third integrated circuitfor converting a high voltage level to a low voltage level.

FIG. 5 is a schematic drawing illustrating a system including anexemplary integrated circuit disposed over a substrate board.

DETAILED DESCRIPTION OF THE DISCLOSURE

A buck converter is used to convert a high voltage to a low voltage thatis deployed to light an LED. A buck converter has a high side driver anda low side driver. An input end of an inductor is electrically coupledto a node between the high side driver and the low side driver. Anoutput end of the inductor is electrically coupled with the LED. Byproviding different voltage states to gates of the high side driver andthe low side driver, energy stored in the inductor can be charged ordischarged through the high side driver and the low side driver,respectively. The energy charge or discharge of the inductor can providea constant voltage on the output end of the inductor.

In a dimming mode, the gate of the high side driver is floating and thelow side driver is turned off. It is found that the current of the LEDmay pull down the voltage level on the node between the high side driverand the low side driver. The pulled-down voltage level may trigger theturn-on of the high side driver, resulting in a current leakage from thepower voltage V_(PP) to the inductor and the LED. The current leakageresults in a power loss and/or a wrong current flowing to the LED

It is understood that the following disclosure provides many differentembodiments, or examples, for implementing different features of thedisclosure. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.Moreover, the formation of a feature on, connected to, and/or coupled toanother feature in the present disclosure that follows may includeembodiments in which the features are formed in direct contact, and mayalso include embodiments in which additional features may be formedinterposing the features, such that the features may not be in directcontact. In addition, spatially relative terms, for example, “lower,”“upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,”“top,” “bottom,” etc. as well as derivatives thereof (e.g.,“horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of thepresent disclosure of one features relationship to another feature. Thespatially relative terms are intended to cover different orientations ofthe device including the features.

FIG. 1A is a schematic drawing illustrating an integrated circuit forconverting a high voltage level to a low voltage level. In FIG. 1A, anintegrated circuit 100 can be a buck converter, a directcurrent-to-direct current (DC-to-DC) converter, or any electricalcircuit that is configured to convert a high voltage level to a lowvoltage level. For example, the electrical circuit can be configured toconvert a high voltage level, e.g., power voltage V_(PP), on a powerline to a low voltage level on a node between an inductor 110 and anelectrical load 130.

In some embodiments, the integrated circuit 100 can include a high sidedriver 101 that is electrically coupled with a low side driver 105. Atleast one electrical load, e.g., an electrical load 130, can be directlyor indirectly electrically coupled with a node N₁ between the high sidedriver 101 and the low side driver 105. A circuit 140 can beelectrically coupled with the high side driver 101 and the node N₁. Thecircuit 140 can be configured to substantially turn off the high sidedriver 101 if the high side driver 101 leaves a cutoff region of thehigh side driver 101 during a tri-state mode.

In some embodiments, the high side driver 101 can be electricallycoupled with a power line that is configured to provide a power voltage,e.g., a power voltage V_(PP). The power voltage V_(PP) can range fromabout tens of volts to about hundreds of volts. The low side driver 105can be electrically coupled with another power line that is configuredto provide a power voltage, e.g., a power voltage V_(SS) or ground. Thepower voltage V_(PP) is higher than the power voltage V_(SS).

In some embodiments, the electrical load 130 can be a light-emittingdiode (LED), a liquid crystal display (LCD) pixel, or any electricaldiode. Though merely showing an electrical load 130 in FIG. 1A, thescope of the present application is not limited thereto. In someembodiments, more than one electrical load can be used. The more thanone electrical load can be electrically coupled with each other in aparallel fashion or in a serial fashion.

In some embodiments using an LED, an inductor 110 and/or a capacitor 120can be electrically coupled with the electrical load 130. The inductor110 can be electrically coupled between the node N₁ and the electricalload 130. The capacitor 120 can be electrically coupled with theelectrical load 130 in a parallel fashion. It is noted that theconfiguration and the number of the inductor 110 and the capacitor 120are merely exemplary. Configurations and numbers of inductors and/orcapacitors may be modified.

In some embodiments using an LED, the operation of the integratedcircuit 100 can include a normal operation mode and a tri-state mode,e.g., a dimming mode. During the normal operation mode, differentvoltage states can be applied to gates of the high side driver 101 andthe low side driver 105. The on/off switching of the high side driver101 and the low side driver 105 can charge or discharge energy stored inthe inductor 110 and/or the capacitor 120. With the energy charge ordischarge of the inductor 110 and/or the capacitor 120, a substantiallyconstant voltage can be provided on the node (not labeled) between theinductor 110 and the electrical load 130 for operations of theelectrical load 130.

During the tri-state mode, the high side driver 101 and the low sidedriver 105 are off. In some embodiments, a clamper 107 can beelectrically coupled between the gate and the source of the high sidedriver 101, clamping the voltage drop, e.g., 5 V, across the gate andthe source of the high side driver 101. The clamper 107 can beconfigured to prevent the gate-source voltage drop that is too high andmay compromise the high side driver 101. In at least this embodiment,the gate of the high side driver 101 can be floating during thetri-state mode, such that the voltage level on the gate of the high sidedriver 101 can follow the voltage level on the source of the high sidedriver 101. In some embodiments, the clamper 107 can be an externaldiode or an intrinsic diode of the high side driver 101. It is notedthat the clamped voltage drop across the gate and source of the highside driver 101 is merely exemplary. The clamped voltage drop can bemodified.

As noted, the circuit 140 can be configured to substantially turn offthe high side driver 101 if the high side driver 101 leaves the cutoffregion during the tri-state mode. In some embodiments, the circuit 140can be configured to sense if the high side driver 101 leaves the cutoffregion of the high side driver 101 during a tri-state mode (step 141 asshown in FIG. 1B). If the high side driver leaves the cutoff region, acurrent leakage may flow from the power voltage V_(PP) to the inductor110 and the capacitor 120 through the high side driver 101.

The circuit 140 can be configured to substantially turn off the highside driver 101 if the high side driver 101 leaves the cutoff regionduring the tri-state mode (step 143 shown in FIG. 1B). By substantiallyturning off the high side driver 101 during the tri-state mode, thepower voltage V_(PP) can be substantially electrically isolated from thenode N₁. The turned-off high side driver 101 can substantially cut offthe leakage path from the power voltage V_(PP) to the inductor 110through the high side driver 101. In some embodiments, the term“substantially turning off the high side driver 101” here can mean thatthe voltage level on the gate of the high side driver 101 can be pulleddown to ground or a power voltage V_(SS) that is lower than the voltagelevel on node N₁. In other embodiments, the term “substantially turningoff the high side driver 101” here can mean that the voltage level onthe gate of the high side driver 101 can be pulled down such that avoltage difference between the gate and source of the high side driver101 is lower than a threshold voltage of the high side driver 101. Byturning off the high side driver 101, a power loss and/or a wrong LEDcurrent resulting from the current leakage on the high side driverduring the tri-state mode can be desirably reduced.

FIG. 2 is a schematic drawing illustrating a second exemplary integratedcircuit for converting a high voltage level to a low voltage level.Items of FIG. 2 that are the same or similar items in FIG. 1A areindicated by the same reference numerals, increased by 100. In FIG. 2, acircuit 240 can include a sensing circuit 250 that can be electricallycoupled with a control circuit 260. In some embodiments, the sensingcircuit 250 can be electrically coupled with a high side driver 201 andthe node N₁. In other embodiments, the sensing circuit 250 can beelectrically coupled with the gate of the high side driver 201. Thesensing circuit 250 can be configured to sense if the high side driver201 leaves its cutoff region during the tri-state mode.

In some embodiments, the sensing circuit 250 can include a currentmirror 251 that can be electrically coupled with at least onetransistor, e.g., transistors 253 and 255. The transistor 253 can beelectrically coupled with the node N₁. In some embodiments, the gate ofthe transistor 253 can be electrically coupled with the gate of the highside driver 201. The transistor 255 can be electrically coupled with thecontrol circuit 260. In some embodiments, the current mirror 251 caninclude a pair of P-type transistors (not labeled). The transistors 253and 255 can be N-type transistors. It is noted that the number and typeof the current mirror 251 and/or the transistors 253 and 255 shown inFIG. 2 are merely exemplary. One skilled in the art can modify thenumber and/or type of the current mirror and/or the transistors toachieve a desired sensing circuit.

Referring again to FIG. 2, the control circuit 260 can be configured tocontrol the high side driver 201 corresponding to the sensing resultfrom the sensing circuit 250 during the tri-state mode. If the high sidedriver 201 does not leave the cutoff region during the tri-state mode,the control circuit 260 is not triggered to turn off the high sidedriver 201. If the high side driver 201 leaves the cutoff region duringthe tri-state mode, the control circuit 260 is triggered to turn off thehigh side driver 201.

In some embodiments, the control circuit 260 can include a currentmirror 261 that can be electrically coupled with the sensing circuit 250and the gate of the high side driver 201. The control circuit 260 canfurther include a switch 263 that can be electrically coupled with anode N₂ between the sensing circuit 250 and the current mirror 261. Insome embodiments, the current mirror 261 can include a pair of N-typetransistors 261 a and 261 b. The switch 263 can be an N-type transistor.It is noted that the number and type of the current mirror 261 and/orthe switch 263 shown in FIG. 2 are merely exemplary. One of skilled inthe art can modify the number and/or type of the current mirror and/orthe switch to achieve a desired control circuit.

During a normal operation mode, the switch 263 can be turned on. Theturned-on switch 263 can electrically couple the node N₂ with a powervoltage, e.g., ground or the power voltage V_(SS). Since the node N₂ canbe substantially grounded, transistors 261 a and 261 b are turned off.The turned-off transistor 261 b can electrically isolate the gate of thehigh side driver 201 from ground or the power voltage V_(SS). Thecircuit 240 is free from interfering with the normal operation of thehigh side driver 201.

During the tri-state mode, the gate of the high side driver 201 can befloating and the low side driver 205 is turned off. A current flowingthrough the electrical load 230 can pull down the voltage level on thenode N₁. Since the gate of the high side driver 201 is floating, thepulled-down voltage node N₁ that is electrically coupled with the sourceof the high side driver 201 may trigger the turn-on of the high sidedriver 201, such that the high side driver 201 leaves the cutoff region.The turned-on high side driver 201 can result in a current leakageflowing from the power voltage V_(PP) to the capacitor 220 through theinductor 210.

In some embodiments, the transistor 253 can be substantially similar tothe high side driver 201. The term “substantially similar to” here meansthat at least one electrical characteristic of the transistor 253 issimilar to that of the high side driver 201. For example, the cutoffregion and/or threshold voltage of the transistor 253 are similar tothose of the high side driver 201. As noted, the gate and source of thetransistor 253 are electrically coupled with the gate and source of thehigh side driver 201, respectively. Not only trigging the turn-on of thehigh side driver 201, the pulled-down voltage level on the node N₁ canalso trigger the turn-on of the transistor 253 during the tri-statemode. The current flowing through the transistor 253 can be as same asor similar to the current leakage flowing through the high side driver201. The current mirror 251 can mirror the current of the transistor 253to the transistor 255. The mirrored current will be provided to thecontrol circuit 260.

During the tri-state mode, the switch 263 of the control circuit 260 isturned off, electrically isolating the node N₂ from the power voltageV_(SS) or ground. As noted, the current flowing through the transistor255 can also flow through the transistor 261 a during the tri-statemode. The current of the transistor 261 a can be mirrored to thetransistor 261 b, which can electrically couple the gate of the highside driver 201 to the power voltage V_(SS) or ground. By pulling downthe voltage level on the gate of the high side driver 201, the high sidedriver 201 can be turned off. The turned-off high side driver 201 cansubstantially cut the leakage path between the power voltage V_(PP) andthe inductor 210. By cutting off the leakage path, the power loss and/orthe wrong current contributed to the turn-on of the high side driver 201during the tri-state mode can be reduced.

In some embodiments, the integrated circuit 200 can optionally include afalse signal filter 270. The false signal filter 270 can be electricallycoupled with the circuit 240. In other embodiments, the false signalfilter 270 can be electrically coupled with the sensing circuit 250 andthe control circuit 260. The false signal filter 270 can be configuredto screen signals that are not representing the tri-state mode. Forexample, signals for driving the high side driver and the low sidedriver may both go low for a short period of time during the normaloperation mode. The signal states during the short period of time do notrepresent the tri-state mode of the integrated circuit 200. The falsesignal filter 270 can screen the signals not representing the tri-statemode.

In some embodiments, the false signal filter 270 can be directly orindirectly electrically coupled with the switch 263 of the controlcircuit 260 and the transistor 255 of the sensing circuit 250. Forexample, the false signal filter 270 can be electrically coupled withthe switch 263 through an inverter 265.

In some embodiments, the false signal filter 270 can include inverters271 and 273, AND gates 275 and 279, and a delay circuit 277. The ANDgate 275 can be electrically coupled with output nodes of the inverters271 and 273. An output node N₃ of the AND gate 275 can be electricallycoupled with the delay circuit 277 and the AND gate 279. An output nodeof the delay circuit 277 can be electrically coupled with the AND gate279. An output node N₄ of the AND gate 279 can be electrically coupledwith the sensing circuit 250 and the control circuit 260.

In some embodiments, the inverters 271 and 273 can receive signal S_(DH)and signal S_(DL) for driving the high side driver 201 and the low sidedriver 205, respectively. The signal S_(DH) and the signal S_(DL) can beused directly or indirectly (e.g., after being processed) to driveand/or control operations of the high side driver 201 and the low sidedriver 205, respectively. In some embodiments, waveforms of the signalS_(DH) and the signal S_(DL) can be shown in FIG. 3. As shown in FIG. 3,the signals S_(DH) and S_(DL) both go low for short time periods duringthe normal operation mode.

The AND gate 275 can perform an AND operation for signals output fromthe inverters 271 and 273, outputting a signal Z_(C1) on the output nodeN₃ of the AND gate 275. The waveform of the signal Z_(C1) can be shownin FIG. 3. As shown in FIG. 3, pulses 301, 303, and 305 indicate theshort time periods during which both of the signals S_(DH) and S_(DL) golow and are signals not representing the tri-state mode. If the pulses301, 303, and 305 were applied to control the circuit 240 during thenormal operation mode, the operations of the circuit 240 would fail.

To make sure that the voltage states of the signals S_(DH) and S_(DL)represents the tri-state mode, the delay circuit 277 can be configuredto delay the signal Z_(C1) for a predetermined period of time. Thedelayed signal is then output to the AND gate 279. The AND gate 279 canbe configured to perform an AND operation for the delay signal from thedelay circuit 277 and the signal Z_(C1), outputting a signal Z_(C) onthe output node N₄ of the AND gate 279. The waveform of the signal Z_(C)can be shown in FIG. 3. As shown in FIG. 3, the time period after astate transition 307 of the signal Z_(C1) can represent the tri-statemode.

Referring again to FIG. 2, during the normal operation mode, the lowvoltage state of the signal Z_(C) can be inverted by the inverter 265 toturn on the switch 263. The turned-on switch 263 can electrically couplethe node N₂ to ground or the power voltage V_(SS). The low voltage stateon the node N₂ can turn off the transistors 261 a and 261 b, such thatthe gate of the high side driver 201 can be electrically isolated fromground or the voltage V_(SS). The low voltage state of the signal Z_(C)can also turn off the transistor 255, such that no current can bemirrored from the transistor 253. From the foregoing, the circuit 240 isfree from interfering the voltage level on the gate of the high sidedriver 201.

During the tri-state mode, the high voltage state of the signal Z_(C)can be inverted by an inverter 265 to turn off the switch 263. Theturned-off switch 263 can electrically isolate the node N₂ from groundor the power voltage V_(SS). The high voltage state of the signal Z_(C)can also turn on the transistor 255, such that the current mirrored fromthe transistor 253 can flow through the transistor 261 a during thetri-state mode. The current of the transistor 261 a is then mirrored tothe transistor 261 b, pulling down the voltage level on the gate of thehigh side driver 201 and turning off the high side driver 201. Theturned-off high side driver 201 can cut off the leakage path between thepower voltage V_(PP) and the inductor 210. By cutting off the leakagepath, the power loss and/or the wrong current due to the turn-on of thehigh side driver 201 during the tri-state mode can be reduced.

FIG. 4 is a schematic drawing illustrating an exemplary integratedcircuit for converting a high voltage level to a low voltage level.Items of FIG. 4 that are the same or similar items in FIG. 1A areindicated by the same reference numerals, increased by 300. In FIG. 4, acircuit 440 can include a transistor 441 that can be electricallycoupled with a switch 443. In some embodiments, the transistor 441 is aP-type transistor and the switch 443 is an N-type transistor. In atleast this embodiment, a gate of the transistor 441 can be electricallycoupled with the node N₁. The source of the transistor 441 can beelectrically coupled with a gate of a high side driver 401. A drain ofthe transistor 441 can be electrically coupled with the switch 443.

In some embodiments, the transistor 441 can be configured to sense ifthe high side driver 401 leaves the cutoff region. For example, duringthe tri-state mode, a gate of the high side driver 401 is floating and alow side driver 405 is turned off. As noted, the voltage level on thenode N₁ may be pulled down due to the current leakage flowing through anelectrical load 430. The pulled-down voltage level on the node N₁ cantrigger the high side driver 401 leaving the cutoff region.

As noted, the gate and the source of the transistor 441 can beelectrically coupled with the node N₁ and the gate of the high sidedriver 401, respectively. The pulled-down voltage level on the N₁ canalso trigger the turn-on of the transistor 441. During the tri-statemode, the switch 443 is turned on. The turned-on switch 443 and theturned-on transistor 441 can electrically couple the gate of the highside driver 401 with ground or the power voltage V_(SS), such that thehigh side driver 401 can be turned off. The turned-off high side driver401 can cut off the leakage path between the power voltage V_(PP) andthe inductor 410. By cutting off the leakage path, the power loss and/orthe wrong current due to the turn-on of the high side driver 401 duringthe tri-state mode can be reduced.

In some embodiments, the integrated circuit 400 can optionally include afalse signal filter 470. In some embodiments, the false signal filter470 can be electrically coupled with the circuit 440. In otherembodiments, the false signal filter 470 can directly or indirectlyelectrically coupled with the switch 443. The false signal filter 470can be configured to screen signals that are not representing thetri-state mode.

In some embodiments, the false signal filter 470 can include a NAND gate471, a delay circuit 473, and an AND gate 475. An output node N₅ of theNAND gate 471 can be electrically coupled with the delay circuit 473 andthe AND gate 475. An output node of the delay circuit 473 can beelectrically coupled with the AND gate 475. An output node N₆ of the ANDgate 475 can be electrically coupled with the circuit 440.

In some embodiments, the NAND gate 471 can receive signals S_(DH)′ andS_(DL)′ for driving high side driver 401 and the low side driver 405,respectively. The signals S_(DH)′ and S_(DL)′ can be used directly orindirectly (e.g., after being processed) to drive and/or controloperations of the high side driver 401 and the low side driver 405,respectively. The waveforms of the signals S_(DH)′ and S_(DL)′ can be assame as or similar to those of signals S_(DH) and S_(DL) shown in FIG.3, respectively.

The NAND gate 471 can perform a NAND operation for the signals S_(DH)′and S_(DL)′, outputting a signal Z_(C1)′ on the output node N₅ of theNAND gate 471. The waveform of the signal Z_(C1)′ can be as same as orsimilar to that of the signal Z_(C1) shown in FIG. 3.

To make sure that the voltage states of the signals S_(DH)′ and S_(DL)′represents the tri-state mode, the delay circuit 473 can be configuredto delay the signal Z_(C1)′ for a predetermined period of time. Thedelayed signal is then output to the AND gate 475. The AND gate 475 canbe configured to perform an AND operation for the delay signal from thedelay circuit 473 and the signal Z_(C1)′, outputting a signal Z_(C)′ onthe output node N₆ of the AND gate 475. The waveform of the signalZ_(C)′ can be as same as or similar to the waveform of the signal Z_(C)shown in FIG. 3.

Referring again to FIG. 4, during the normal operation mode, the lowvoltage state of the signal Z_(C)′ can turn off the switch 443. Theturned-off switch 443 can electrically isolate the transistor 441 fromground or a power voltage V_(SS), such that the circuit 440 is free frominterfering with the normal operation of the high side driver 401.

As noted, if the high side driver 401 leaves the cutoff region duringthe tri-state mode, the transistor 441 can be turned on. During thetri-sate mode, the high state of the signal Z_(C)′ can turn on theswitch 443. The turned-on switch 443 can electrically couple the drainof the transistor 441 with ground or the power voltage V_(SS). Theturned-on transistor 441 and switch 443 can electrically couple the gateof the high side drive 401 with ground or the power voltage V_(SS), suchthat the high side driver 401 is turned off. The turned-off high sidedriver 401 can cut off the leakage path between the power voltage V_(PP)and the inductor 410. By cutting off the leakage path, the power lossand/or the wrong current due to the turn-on of the high side driver 401during the tri-state mode can be reduced.

It is noted that the configurations of the false signal filters 270 and470 are merely exemplary. Configurations and types of logic gates and/ordelay circuits of the false signal filters 270 and 470 can be changed.In some embodiments, additional logic gates and/or diodes can be addedto achieve the purpose of screening signals that do not represent thetri-state mode. In some embodiments, the false signal filter 470 can beused to replace the false signal filter 270 of the integrated circuit200, vice versa.

FIG. 5 is a schematic drawing illustrating a system including anexemplary an integrated circuit disposed over a substrate board. In FIG.5, a system 500 can include an integrated circuit 502 disposed over asubstrate board 501. The substrate board 501 can include a printedcircuit board (PCB), a printed wiring board and/or other carrier that iscapable of carrying an integrated circuit. In some embodiments, theintegrated circuit 502 can be similar to one of the integrated circuits100, 200, and 400 described above in conjunction with FIGS. 1-2 and 4,respectively. The integrated circuit 502 can be electrically coupledwith the substrate board 501. In some embodiments, the integratedcircuit 502 can be electrically and/or thermally coupled with thesubstrate board 501 through bumps 505. The system 500 can be part of anelectronic system such as displays, panels, lighting systems, autovehicles, entertainment devices, or the like. In some embodiments, thesystem 500 including the integrated circuit 502 can provides an entiresystem in one IC, so-called system on a chip (SOC) or system onintegrated circuit (SOIC) devices.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. An integrated circuit for converting a highvoltage level to a low voltage level, the integrated circuit comprising:a high side driver; a low side driver electrically coupled with the highside driver; and a circuit electrically coupled with the high sidedriver and a first node between the high side driver and the low sidedriver, wherein the circuit is configured to substantially turn off thehigh side driver if the high side driver leaves a cutoff region of thehigh side driver during a tri-state mode.
 2. The integrated circuit ofclaim 1, wherein the circuit comprises: a sensing circuit electricallycoupled with the high side driver and the first node, wherein thesensing circuit is configured to sense if the high side driver leavesthe cutoff region of the high side driver during the tri-state mode; anda control circuit electrically coupled with the sensing circuit, whereinthe control circuit is configured to control the high side drivercorresponding to the sensing result from the sensing circuit during thetri-state mode.
 3. The integrated circuit of claim 2, wherein thesensing circuit comprises: a first current mirror; and a firsttransistor electrically coupled with the first current mirror and thefirst node, wherein a gate of the first transistor is electricallycoupled with a gate of the high side driver; and a second transistorelectrically coupled with the first current mirror and the controlcircuit.
 4. The integrated circuit of claim 2, wherein the controlcircuit comprises: a second current mirror electrically coupled with thesensing circuit and a gate of the high side driver; and a switchelectrically coupled with a second node between the second currentmirror and the sensing circuit, wherein the switch is configured toelectrically couple the second node with a ground voltage during anon-tri-state mode.
 5. The integrated circuit of claim 1, wherein thecircuit comprises: a third transistor, wherein a gate of the thirdtransistor is electrically coupled with the first node, and a source ofthe third transistor is electrically coupled with a gate of the highside driver; and a switch electrically coupled with a drain of the thirdtransistor.
 6. The integrated circuit of claim 1, further comprising: afalse signal filter electrically coupled with the circuit, wherein thefalse signal filter is configured to screen signals that are notrepresenting the tri-state mode.
 7. The integrated circuit of claim 6,wherein the false signal filter comprises: a pair of inverters; a firstAND gate electrically coupled with output ends of the inverters; a delaycircuit electrically coupled with an output end of the first AND gate;and a second AND gate electrically coupled with an output end of thedelay circuit and the output end of the first AND gate.
 8. Theintegrated circuit of claim 6, wherein the false signal filtercomprises: a NAND gate; a delay circuit electrically coupled with anoutput end of the NAND gate; and an AND gate electrically coupled withan output end of the delay circuit and the output end of the NAND gate.9. An integrated circuit for converting a high voltage level to a lowvoltage level, the integrated circuit comprising: a high side driverelectrically coupled with a power line that is configured to provide afirst power voltage; a low side driver electrically coupled with thehigh side driver and a power line that is configured to provide a secondpower voltage; an inductor electrically coupled with a first nodebetween the high side driver and the low side driver; a capacitorelectrically coupled with the inductor; and a sensing circuitelectrically coupled with the high side driver and the first node,wherein the sensing circuit is configured to sense if the high sidedriver leaves a cutoff region of the high side driver during thetri-state mode; and a control circuit electrically coupled with thesensing circuit, wherein the control circuit is configured to turn offthe high side driver if the high side driver leaves the cutoff regionduring the tri-state mode.
 10. The integrated circuit of claim 9,wherein the sensing circuit comprises: a first current mirror; and afirst transistor electrically coupled with the first current mirror andthe first node, wherein a gate of the first transistor is electricallycoupled with a gate of the high side driver; and a second transistorelectrically coupled with the first current source and the controlcircuit.
 11. The integrated circuit of claim 9, wherein the controlcircuit comprises: a second current mirror electrically coupled with thesensing circuit and a gate of the high side driver; and a switchelectrically coupled with a second node between the second currentmirror and the sensing circuit, wherein the switch is configured toelectrically couple the second node with a ground voltage during anon-tri-state mode.
 12. The integrated circuit of claim 9, furthercomprising: a false signal filter electrically coupled with the sensingcircuit and the control circuit, wherein the false signal filter isconfigured to screen signals that are not representing the tri-statemode.
 13. The integrated circuit of claim 12, wherein the false signalfilter comprises: a pair of inverters; a first AND gate electricallycoupled with output ends of the inverters; a delay circuit electricallycoupled with an output end of the first AND gate; and a second AND gateelectrically coupled with an output end of the delay circuit and theoutput end of the first AND gate.
 14. The integrated circuit of claim12, wherein the false signal filter comprises: a NAND gate; a delaycircuit electrically coupled with an output end of the NAND gate; and anAND gate electrically coupled with an output end of the delay circuitand the output end of the NAND gate.
 15. An integrated circuit forconverting a high voltage level to a low voltage level, the integratedcircuit comprising: a high side driver electrically coupled with a powerline that is configured to provide a first power voltage; a low sidedriver electrically coupled with the high side driver and a power linethat is configured to provide a second power voltage; an inductorelectrically coupled with a first node between the high side driver andthe low side driver; a capacitor electrically coupled with the inductor;and a circuit electrically coupled with the first node and the high sidedriver, wherein the circuit comprises: a transistor, wherein a gate ofthe transistor is electrically coupled with the first node and a sourceof the transistor is electrically coupled with a gate of the high sidedriver; and a switch, wherein the switch is electrically coupled betweenthe transistor and the power line that is configured to provide a secondpower voltage.
 16. The integrated circuit of claim 15, wherein thecircuit is configured to substantially turn off the high side driver ifthe high side driver leaves a cutoff region of the high side driverduring a tri-state mode.
 17. The integrated circuit of claim 16, furthercomprising: a false signal filter electrically coupled with the switch,wherein the false signal filter is configured to screen signals that arenot representing the tri-state mode.
 18. The integrated circuit of claim17, wherein the false signal filter comprises: a pair of inverters; afirst AND gate electrically coupled with output ends of the inverters; adelay circuit electrically coupled with an output end of the first ANDgate; and a second AND gate electrically coupled with an output end ofthe delay circuit and the output end of the first AND gate.
 19. Theintegrated circuit of claim 17, wherein the false signal filtercomprises: a NAND gate; a delay circuit electrically coupled with anoutput end of the NAND gate; and an AND gate electrically coupled withan output end of the delay circuit and the output end of the NAND gate.